Energy-Efficient Communication Processors: Design and by Robert Fasthuber, Francky Catthoor, Praveen Raghavan,

By Robert Fasthuber, Francky Catthoor, Praveen Raghavan, Frederik Naessens

This publication describes a brand new layout strategy for energy-efficient, Domain-Specific guideline set Processor (DSIP) architectures for the instant baseband area. The leading edge suggestions offered permit co-design of algorithms, architectures and expertise, for effective implementation of the main complicated applied sciences. to illustrate the feasibility of the author’s layout method, case reviews are incorporated for an important performance of complex instant structures with elevated computational functionality, flexibility and reusability. Designers utilizing this process will make the most of lowered development/product expenditures and larger scalability to destiny approach know-how nodes.

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5 a General system design flow and b illustrative example for the implementation of the physical layer functionality. Analog/Digital hardware block available at this point, pessimistic assumptions are made. To limit the design complexity, the functional blocks are typically implemented with standard algorithms and floating-point arithmetic. At this phase, the link to hardware is rather weak, therefore throughput and latency requirements are largely neglected. 2 Algorithm Design During this second phase, the functional blocks are implemented with algorithms that are better suited for implementation.

6 Other Styles FPGAs, GPUs and general purpose CPUs are also sometimes used for wireless implementations (especially in academia and for prototyping). However, they are clearly not sufficiently energy effective and also not cost effective for the targeted physical layer consumer application domain. For this reason we do not further review and consider them in this book. 3 Background on the Physical Layer System Design In this section the general physical layer system design flow is described. More details and more references will be provided in the Sects.

Synchronization (Spatial) MIMO Detection Symbol Demap. Symbol Deinterl. Symbol Demap. Symbol Deinterl. Spatial Cyclic Prefix Removal Outer Modem FEC Depuncturing Deinterleaving Decoding Channel Est. + Preprocessing Fig. 2 Functional blocks of a typical wide-band OFDM MIMO receiver, which can perform the physical layer signal processing of modern wireless communication systems. The functional blocks with the highest computational complexity, from the digital domain, are typically the channel filter in the Digital Front-End (DFE), the Fast Fourier Transformation (FFT) and the MIMO detector in the inner modem and the Forward Error Correction (FEC) decoder in the outer modem computes parameters, such as time and frequency offset, which are then used for the payload signal processing.

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