EDA for IC System Design, Verification, and Testing by Louis Scheffer, Luciano Lavagno, Grant Martin

By Louis Scheffer, Luciano Lavagno, Grant Martin

Offering a entire evaluation of the layout automation algorithms, instruments, and methodologies used to layout built-in circuits, the Electronic layout Automation for built-in Circuits Handbook comes in volumes. the 1st quantity, EDA for IC process layout, Verification, and Testing, completely examines system-level layout, microarchitectural layout, logical verification, and trying out. Chapters contributed by way of prime specialists authoritatively speak about processor modeling and layout instruments, utilizing functionality metrics to choose microprocessor cores for IC designs, layout and verification languages, electronic simulation, acceleration and emulation, and lots more and plenty extra. store at the entire set.

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Dynamic power management. 8. Static power management (leakage). A series of novel design and transistor innovations can reduce the power consumption. These include operand isolation, clock gating, and voltage-islands. Timing and power considerations are very often in conflict with each other, so the design team must employ these remedies carefully. A design can have part of its logic clock-gated by using logic to enable the bank of registers. The logic driven by the registers is quiescent until the clock-gated logic enables the registers.

These effects can produce erratic behavior for chips manufactured in smaller geometries. Issues such as crosstalk, IR drop, and electromigration are factors that the design team must consider in order to produce circuits that perform correctly. Crosstalk noise can occur when two wires are close to each other (cf. 6). One wire, the aggressor, switches while the victim signal is in a quiet state or making an opposite transition. In this case, the aggressor can force the victim to glitch. This can cause a functional failure or can simply consume additional power.

Moorby, The Verilog Hardware Description Language, Kluwer Academic Publishers, Dordrecht, 1996. [4] D. Pellerin and D. , 1996. [5] S. Sutherland, S. Davidson, and P. Flake, SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, Kluwer Academic Publishers, Dordrecht, 2004. [6] T. Groetker, S. Liao, G. Martin, and S. Swan, System Design with SystemC, Kluwer Academic Publishers, Dordrecht, 2002. [7] G. Peterson, P. Ashenden, and D. Teegarden, The System Designer’s Guide to VHDL-AMS, Morgan Kaufman Publishers, San Francisco, CA, 2002.

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